以VHDL實現數字時鐘

Question

我正在嘗試使用VHDL製作數字時鐘，並且我想在VGA屏幕上顯示結果。但我堅持這樣的想法，即如何將整數類型轉換爲BCD？因爲現在我正在將小時，分鐘和秒數據作爲一個整數，我會實現它，以便我可以以最充分的方式在我的VGA組件中使用它。你會對此有何建議？

在此先感謝！

Answer 1

你是什麼意思「以最充分（高效？）的方式實施」？你的意思是不使用32位X 3來存儲時間？

它是否必須在BCD？你可以限制你的整數的大小：5位爲小時，對於分鐘6位，6位，第二：

SIGNAL hour: INTEGER RANGE 0 TO 23; 
SIGNAL minute: INTEGER RANGE 0 TO 59; 
SIGNAL second: INTEGER RANGE 0 TO 59; 

如果他們都需要在一個變量，你可以把他們都轉換成17位的位向量。

SIGNAL time: BIT_VECTOR(16 DOWNTO 0); 
time(16 DOWNTO 12) <= hour; 
time(11 DOWNTO 6) <= minute; 
time(5 DOWNTO 0) <= second; 

Answer 2

如果你想單獨定時器，你可以使用除法和模運算符來將整數轉換爲BCD。但是，這很可能會相當糟糕。你可能只是實現六個計數器來代替，這樣的事情：

library ieee; 
use ieee.std_logic_1164.all; 

entity clock is 
     port (
       resetAX : in std_logic; -- Asynchronous reset, active low 
       clk : in std_logic; -- Clock signal, runs faster than 1/second 
       second_enable : in std_logic; -- Signal active (high) only when seconds to be incremented 
       h_ms : out std_logic_vector(1 downto 0); -- MS digit of hour (0, 1, 2) 
       h_ls : out std_logic_vector(3 downto 0); -- LS digit of hour (0-9) 
       m_ms : out std_logic_vector(2 downto 0); -- MS digit of minute (0-5) 
       m_ls : out std_logic_vector(3 downto 0); -- LS digit of minute (0-9) 
       s_ms : out std_logic_vector(2 downto 0); -- MS digit of second (0-5) 
       s_ls : out std_logic_vector(3 downto 0) -- LS digit of second (0-9) 
     ); 
end clock; 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

architecture rtl of clock is 
     signal h_ms_int : integer range 0 to 2; 
     signal h_ls_int : integer range 0 to 9; 
     signal m_ms_int : integer range 0 to 5; 
     signal m_ls_int : integer range 0 to 9; 
     signal s_ms_int : integer range 0 to 5; 
     signal s_ls_int : integer range 0 to 9; 
begin 

     COUNT: process(resetAX, clk) 
     begin 
       if resetAX = '0' then 
         h_ms_int <= 0; 
         h_ls_int <= 0; 
         m_ms_int <= 0; 
         m_ls_int <= 0; 
         s_ms_int <= 0; 
         s_ls_int <= 0; 
       elsif clk'event and clk='1' then 
         if second_enable = '1' then 
           if s_ls_int = 9 then 
             if s_ms_int = 5 then 
               if m_ls_int = 9 then 
                 if m_ms_int = 5 then 
                   if (h_ls_int = 9 or (h_ls_int=3 and h_ms_int=2)) then 
                     if (h_ls_int=3 and h_ms_int=2) then 
                       h_ms_int <= 0; 
                     else 
                       h_ms_int <= h_ms_int + 1; 
                     end if; 
                     h_ls_int <= 0; 
                   else 
                     h_ls_int <= h_ls_int + 1; 
                   end if; 
                   m_ms_int <= 0; 
                 else 
                   m_ms_int <= m_ms_int + 1; 
                 end if; 
                 m_ls_int <= 0; 
               else 
                 m_ls_int <= m_ls_int + 1; 
               end if; 
               s_ms_int <= 0; 
             else 
               s_ms_int <= s_ms_int + 1; 
             end if; 
             s_ls_int <= 0; 
           else 
             s_ls_int <= s_ls_int + 1; 
           end if; 
         end if; 
       end if; 
     end process COUNT; 

     h_ms <= std_logic_vector(to_unsigned(h_ms_int, h_ms'length)); 
     h_ls <= std_logic_vector(to_unsigned(h_ls_int, h_ls'length)); 
     m_ms <= std_logic_vector(to_unsigned(m_ms_int, m_ms'length)); 
     m_ls <= std_logic_vector(to_unsigned(m_ls_int, m_ls'length)); 
     s_ms <= std_logic_vector(to_unsigned(s_ms_int, s_ms'length)); 
     s_ls <= std_logic_vector(to_unsigned(s_ls_int, s_ls'length)); 

end rtl; 

這些都是非常小的計數器，所以它不應該過於龐大，即使稍微複雜的包裝邏輯。由於我沒有這裏提供的任何綜合工具，我無法檢查在家裏的大小，但我預計它應該小於十分和十模邏輯。