我遇到一個更多的困難,同時將fifo代碼實例化到我的頂級模塊。我想從我的串行端口(接收子系統)存儲一些數據集,例如「歡迎來到FPGA的世界」,然後我想要找回它說按下fpga板上的按鈕或FIFO已滿時。我寫了我的fifo代碼和串行通信代碼。想法是從鍵盤 - >接收子系統 - > FIFO - >傳輸子系統 - >超級終端發送的數據。目前我正在使用8位寬的fifo,並說28深,只是爲了存儲一些小數據。請在這方面幫助我,我該如何實現它。我有來自保存在register_save中的接收器的字節。 fifo codeFIFO實現 - VHDL
inst_bit8_recieve_unit : entity work.byte_recieve_8N1
port map (ck => ck,
reset => reset,
new_byte_in_buffer => new_byte_in_buffer,
byte_read_from_buffer => byte_read_from_buffer,
recieve_buffer => register_save,
JA_2 => JA(2));
---------------------FIFO instantiate-------------------------------
inst_of_fifo_Recieve_unit : entity work.fifo
generic map (B => data_bits, W => fifo_width)
port map (ck => ck,
reset => reset,
rd => rd_rx,
wr => wr_rx,
write_data => num_recieved,
read_data => num_recieved_fifo,
empty => empty_rx,
full => full_rx);
inst_bit8_transmit_unit : entity work.byte_transmit_8N1
port map (ck => ck,
reset => reset,
send_byte_ready => send_byte_ready,
send_byte_done => send_byte_done ,
send_buffer => num_send,
JAOUT_0 => JAOUT);
proc_send5byte: process(ck, reset, state_byte5, send_byte_done, num_send, state_button_0, num_recieved_fifo, rd_rx)
begin
if reset = '1' THEN
state_byte5 <= idle;
send_byte_ready <='0';
num_send <= "00000000" ;
else
if rising_edge(ck) then
case state_byte5 is
when idle => ---- in this, if btn(0) is high i.e pressed then only state_byte5 will go to next state
if state_button_0 = transit_pressed then
state_byte5 <= byte;
end if;
-----===============================================================
when byte =>
if (not empty_rx = '1') then
if send_byte_ready ='0' and send_byte_done = '0' then ----here if condition is satified the send_byte_ready will be set
send_byte_ready <='1'; --------- shows next byte is ready
num_send <= num_recieved_fifo;
rd_rx <='1';
end if;
end if;
if send_byte_ready = '1' and send_byte_done = '1' then --- during load state send_byte will be resets
send_byte_ready <='0';
rd_rx <= '0';
state_byte5 <= idle; ----------- go back to idle
end if;
--end if;
---===============================================================
when others =>
state_byte5 <= idle; ------------- for other cases state state _byte5 will be in idle
send_byte_ready <= '0';
rd_rx <= '0';
end case;
end if;
end if;
end process;
proc_recieving_byte : process (ck, reset, register_save, new_byte_in_buffer, full_rx, num_recieved, wr_rx)
begin
if reset = '1' then
byte_read_from_buffer <= '0';
else
if rising_edge(ck) then
if full_rx = '0' then
if new_byte_in_buffer = '1' and byte_read_from_buffer = '0' then
byte_read_from_buffer <= '1';
wr_rx <= '1';
num_recieved(7 downto 0) <= register_save(7 downto 0);
end if;
end if;
if new_byte_in_buffer = '0' then
byte_read_from_buffer <= '0';
wr_rx <= '0';
end if;
--end if;
end if;
end if;
end process;
現在只是補充更正後的代碼,這似乎是工作。問題araises增加fifo的深度時。當深度> 2時,則每三個字節都丟失。 請幫忙,爲什麼我丟失數據。
如果您有關於某些特定代碼的具體問題,請詢問並且有人會很樂意回答。但這不是一個代碼寫入服務。 –
嗨。我理解你的話。但我需要幫助增加或追加收到的字節,直到fifo充滿。這一部分讓我感到困惑,我是否應該每次檢查FIFO的深度,同時保存字節,否則它會自行保存,直到它已滿。 – skale
這個問題完全不可理解。請閱讀[我如何問一個好問題](https://stackoverflow.com/help/how-to-ask)。 – JHBonarius