VHDL仿真錯誤：「delta計數溢出」

Question

run 50 ns
#KERNEL: stopped at delta: 5000 at time 10 ns.
#KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
#Error: Fatal error occurred during simulation.

我在哪裏錯了？

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
entity funct is 
    port(x: in std_logic_vector (2 downto 1); 
    y: out std_logic); 
end funct; 

architecture funct of funct is 
    signal r, s, q : std_logic_vector(2 downto 0) := "000"; 
begin 
    process 
    begin 
     wait on x, q; 
     r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1))); 
     r(1) <= q(2) and not(x(2)); 
     r(0) <= not(q(1)) and q(0) and x(1); 
     s(2) <= q(1) and x(2); 
     s(1) <= not(q(2)) and q(0) and not(x(2)); 
     s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2); 
    end process; 

    y <= q(2) and not(q(1)) and q(0); 

    process 
    begin 
     wait on r, s; 
     q(0) <= s(0) or (not(r(0)) and q(0)); 
     q(1) <= s(1) or (not(r(1)) and q(1)); 
     q(2) <= s(2) or (not(r(2)) and q(2)); 
    end process; 
end funct; 

Answer 1

這兩個過程觸發器彼此以一種循環方式：

• 當x最初改變，它會觸發第一個進程，
• r和s由第一工序中會產生，
• 這些用於wait第二個過程，
• 然後生成q，
• 什麼是在第一過程

的所以先執行，第二，第一，...進程繼續不受時間增量的wait使用，但與delta計數器的增量，直到達到三角洲計數器限制，並且您會看到您看到的錯誤。

要解決這個問題，您需要更正組合邏輯以避免內部循環。

此外，與等待類似像信號的過程：

process is 
begin 
    ... 
    wait on {signals}; 
end process; 

通常是這樣寫的：

process ({signals}) is 
begin 
    ... 
end process; 

如果純粹的組合邏輯寫入的過程中，那麼實際上你可以跳過製作一個過程，所以你的代碼可以這樣寫：

r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1))); 
r(1) <= q(2) and not(x(2)); 
r(0) <= not(q(1)) and q(0) and x(1); 
s(2) <= q(1) and x(2); 
s(1) <= not(q(2)) and q(0) and not(x(2)); 
s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2); 

y <= q(2) and not(q(1)) and q(0); 

q(0) <= s(0) or (not(r(0)) and q(0)); 
q(1) <= s(1) or (not(r(1)) and q(1)); 
q(2) <= s(2) or (not(r(2)) and q(2)); 

並寫代碼th很清楚地揭示了從q(0)到r(0)到q(0)的組合循環。