所以我試圖設計七段解碼器。當在110按下按鈕時,LED顯示器應顯示1位十六進制數字:0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F。但是,當在101按下按鈕時,LED顯示器應該顯示1位十進制數:0,1,2,3,4,5,6,7,8,9。七段解碼器
這是我的警告:
Xst:737 - Found 1-bit latch for signal <out<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <out<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
這是使用賽靈思設計工具我的代碼:
module hex_sch(out, in, button);
output reg [6:0] out;
input [3:0] in;
input [2:0] button;
// Low active signal should activate the LEDs
always @(button or in)
begin
if (button == 3'b110) begin
case (in)
//Output format gfedcba
4'h0: out <= 7'b1000000;
4'h1: out <= 7'b1111001;
4'h2: out <= 7'b0100100;
4'h3: out <= 7'b0110000;
4'h4: out <= 7'b0011001;
4'h5: out <= 7'b0010010;
4'h6: out <= 7'b0000010;
4'h7: out <= 7'b1111000;
4'h8: out <= 7'b0000000;
4'h9: out <= 7'b0011000;
4'hA: out <= 7'b0001000;
4'hB: out <= 7'b0000011;
4'hC: out <= 7'b1000110;
4'hD: out <= 7'b0100001;
4'hE: out <= 7'b0000110;
4'hF: out <= 7'b0001110;
default: out <= 7'bx;
endcase
end
else if (button == 3'b101) begin
case (in)
//Output format abcdefg
4'd0: out <= 7'b1000000;
4'd1: out <= 7'b1111001;
4'd2: out <= 7'b0100100;
4'd3: out <= 7'b0110000;
4'd4: out <= 7'b0011001;
4'd5: out <= 7'b0010010;
4'd6: out <= 7'b0000010;
4'd7: out <= 7'b1111000;
4'd8: out <= 7'b0000000;
4'd9: out <= 7'b0011000;
default out <= 7'bx;
endcase
end
end
endmodule
這真的取決於你想要如何正確地解決這個問題。如果按鈕設置爲3'b000,會發生什麼?你目前的設計是推斷鎖存器(這可能是你想要的?),因爲如果不是組合的邏輯給出(即按鈕的情況是3'b000,應該是什麼?)。理想情況下,如果確實需要鎖存器(例如,如果按鈕變爲3'b000,則不需要保存其值),則應該更明確地設置代碼。另外,你需要特定的情況下,擺脫你的非阻塞任務....所有這取決於你想要發生的其他按鈕值。 – Unn 2014-10-16 20:23:03