我是初學者,但仍然不能相信我不能使這麼簡單的代碼工作。 我有Digilent Nexys2 FPGA,編程xilinx ISE 我的目標是在兩個不同的七段顯示器上打印數字「2」和「1」(我想用我的眼睛看它「21」。A,B,C ,D,E,F,G,P是顯示器(kathodes)的LED,AN0和AN1是顯示器的陽極,0將它們打開)。在七段顯示器上寫數字的簡單流程問題
我試圖在那裏投資的邏輯是,FPGA會很快重複這個'過程',以至於我的眼睛只能檢測到光線。 我認爲我應該把clk放在進程敏感列表中的原因是,每當時鐘改變時,它都會進入進程並執行我的命令,對嗎? 我在這裏犯了什麼邏輯錯誤? 我試圖讓如果其他語句如果rising_edge(clk)然後「1」將顯示其他「2」,但它仍然導致一些錯誤..什麼?我應該讓這個過程時鐘?
這裏是警告我得到時,我想合成它
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
這裏是我得到當我嘗試生成一個編程位文件警告
WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal does not drive any load pins in the design.
WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal does not drive any load pins in the design.
和
這裏是UCF文件:
NET "clk" LOC = B8;
NET "A" LOC = L18;
NET "B" LOC = F18;
NET "C" LOC = D17;
NET "D" LOC = D16;
NET "E" LOC = G14;
NET "F" LOC = J17;
NET "G" LOC = H14;
NET "P" LOC = C17;
NET "AN0" LOC = F17;
NET "AN1" LOC = H17;
NET "AN2" LOC = C18;
NET "AN3" LOC = F15;
和來這裏的代碼本身:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity disp is
Port (
clk : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC;
C : out STD_LOGIC;
D : out STD_LOGIC;
E : out STD_LOGIC;
F : out STD_LOGIC;
G : out STD_LOGIC;
P : out STD_LOGIC;
AN0 : out STD_LOGIC;
AN1 : out STD_LOGIC;
AN2 : out STD_LOGIC;
AN3 : out STD_LOGIC
);
end disp;
-- main idea: writing "21" on seven segment display.
architecture BEHAV of disp is
begin
process (clk)
begin
--writing '1' (AN0 is on)
AN0 <='0';
AN1 <='1';
AN2 <='1';
AN3 <='1';
A <='1';
B <='0';
C <='0';
D <='1';
E <='1';
F <='1';
G <='1';
P <='1';
--writing '2' (AN1 is on)
AN0 <='1';
AN1 <='0';
AN2 <='1';
AN3 <='1';
A <='0';
B <='0';
C <='1';
D <='0';
E <='0';
F <='1';
G <='0';
P <='1';
end process;
end BEHAV;
你說得對,'1'和'2'互相干涉/放在一起。像這兩個數字的所有LED同時亮起。 這是爲什麼? ,因爲直到分配完成後,FPGA再次進入該過程?所以它沒有完成?或什麼地獄:D 我應該給這種延遲(在分配後(與使用計數器也許)或類似的東西「不要繼續,直到我完成這個分配」命令?)?怎麼樣? @Morten Zilmer – TsotneP 2014-09-27 22:48:53