vhdl乘法器

Question

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity Lab3_Adder1 is 
    Port (cin : in STD_LOGIC; 
      a : in STD_LOGIC_VECTOR (3 downto 0); 
      b : in STD_LOGIC_VECTOR (3 downto 0); 
      s : out STD_LOGIC_VECTOR (3 downto 0); 
      cout : out STD_LOGIC); 
end Lab3_Adder1; 

architecture Behavioral of Lab3_Adder1 is 

    SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0); 

begin 
    c(0) <= cin; 
    s <= a XOR b XOR c (3 DOWNTO 0); 
    c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0)); 
    cout <= c(4); 
end Behavioral; 

你好，這是我第一次使用這個論壇。我在VHDL上做了華萊士樹乘法。上面的代碼是完整加法器的代碼。我想知道我們如何在主代碼中調用函數/組件？ （如在C編程中）。我會在我的主代碼中調用這個完整的加法器。

Answer 1

您可以像在C中一樣調用VHDL中的函數 - 既可以初始化常量，信號或變量，也可以作爲過程中的順序語句。但是這個並不重要。

但是你不叫組件！這就像在C++中調用一個對象 - 它絕對沒有意義！

在VHDL中，您可以實例化組件或（更簡單！）實體，並使用信號互連其端口。這（非常粗暴地）更像是以面向對象的語言來聲明對象和發送消息。這就是所謂的「結構性VHDL」，經常出現在VHDL設計的頂尖水平，創建和CPU，內存接口，FFT處理器等

互連元件鑑於你的實體

entity Lab3_Adder1 is 
    Port (cin : in STD_LOGIC; 
      a : in STD_LOGIC_VECTOR (3 downto 0); 
      b : in STD_LOGIC_VECTOR (3 downto 0); 
      s : out STD_LOGIC_VECTOR (3 downto 0); 
      cout : out STD_LOGIC); 
end Lab3_Adder1; 

我可以建立例如一個8位加法器，如下所示：

entity Adder_8bit is 
    Port (cin : in STD_LOGIC; 
      a : in STD_LOGIC_VECTOR (7 downto 0); 
      b : in STD_LOGIC_VECTOR (7 downto 0); 
      s : out STD_LOGIC_VECTOR (7 downto 0); 
      cout : out STD_LOGIC); 
end Adder_8bit; 

architecture Structural of Adder_8bit is 

signal carry_int : std_logic; -- between lower and upper halves 

begin 
-- We need to create and connect up two adders 

LSB_adder : entity work.Lab3_Adder1 
    Port Map( 
      cin => cin, 
      a => a(3 downto 0), 
      b => b(3 downto 0), 
      s => s(3 downto 0), 
      cout => carry_int 
    ); 
MSB_adder : entity work.Lab3_Adder1 
    Port Map( 
      cin => carry_int, 
      a => a(7 downto 4), 
      b => b(7 downto 4), 
      s => s(7 downto 4), 
      cout => cout 
    ); 

end Structural; 

Answer 2

可以定義VHDL-功能，其取代組合電路並且其可以在主VHDL碼類似於C的功能的任何地方被調用。

您需要首先在函數定義所在的位置定義一個包。

======= myAdders.vhdl ==============

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 

package myAdders is 

function Lab3_Adder1(cin : in STD_LOGIC; 
a : in STD_LOGIC_VECTOR (3 downto 0); 
b : in STD_LOGIC_VECTOR (3 downto 0); 
s : out STD_LOGIC_VECTOR (3 downto 0)) return std_logic; 
end Lab3_Adder1; 

end myAdders; 

package body myAdders is 


function Lab3_Adder1 (cin : in STD_LOGIC; 
a : in STD_LOGIC_VECTOR (3 downto 0); 
b : in STD_LOGIC_VECTOR (3 downto 0); 
s : out STD_LOGIC_VECTOR (3 downto 0)) return std_logic is 
variable c: std_logic_vector(4 downto 0); 
begin 

c(0) := cin; 
s := a XOR b XOR c (3 DOWNTO 0); 
c (4 DOWNTO 1) := (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0)); 
return c(4); 
end Lab3_Adder1; 


end myAdders; 

======= topLevel.vhdl ===== =========

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
use work.myAddres.all; 


entity TopLevel is 
    Port ( 
      cin : in STD_LOGIC; 
      a : in STD_LOGIC_VECTOR (3 downto 0); 
      b : in STD_LOGIC_VECTOR (3 downto 0); 
      c : out STD_LOGIC_VECTOR (3 downto 0) 
      ); 
end TopLevel; 

architecture Structural of TopLevel is 

signal carry : std_logic; 

begin 

carry <= Lab3_Adder1(cin, a, b, c); 

... and so on ... 

end Structural;