遞歸自我實例化組件[VHDL]

Question

我開始使用VHDL開發一個大型項目，我希望每個基本組件（加法器，多路複用器，寄存器......）寫得儘可能的有序。

我正在考慮爲每個實體使用不同的體系結構（通過不同的抽象層或不同類型的實現），然後使用配置選擇一個。

我的問題是：是否有可能遞歸自我實例化一個組件，但具有不同的配置？

例如，讓我們的加法：

entity ADDER is 
    generic(...); 
    port(...); 
end entity ADDER; 

然後我想有不同的架構，例如：

-- Behavioral Add 
architecture BHV of ADDER is 
    out <= A + B; 
end architecture BHV; 


-- Ripple Carry Adder 
architecture RCA of ADDER is 
    ... 
end architecture RCA; 


-- Carry Select Adder 
architecture CSA of ADDER is 
    component ADDER -- <== this should be configured as RCA 
    ... 
end architecture CSA; 

是否有可能配置中使用的加法器攜帶選擇與漣漪攜帶沒有結束在無限實例化循環？

Answer 1

是的，可以使用Ripple Carry配置在進位選擇內部使用的加法器，而不必在無限實例化循環中結束。通過遞歸實例，終止條件是必需的 - 這是一種終止遞歸的東西。配置正在執行該角色。

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all; 

entity ADDER is 
    generic(WIDTH : positive := 8); 
    port(CIN : in std_logic; 
     A : in std_logic_vector(WIDTH-1 downto 0); 
     B : in std_logic_vector(WIDTH-1 downto 0); 
     F : out std_logic_vector(WIDTH-1 downto 0); 
     COUT : out std_logic); 
end entity ADDER; 

-- Ripple Carry Adder 
architecture RCA of ADDER is 
    signal CIN0 : unsigned(0 downto 0); 
    signal FIN : unsigned(WIDTH downto 0); 
begin 
    CIN0(0) <= CIN; 
    FIN <= resize(unsigned(A), WIDTH+1) + resize(unsigned(B), WIDTH+1) + CIN0; -- yes, I know it's not a ripple carry adder 
    F <= std_logic_vector(FIN(WIDTH-1 downto 0)); 
    COUT <= FIN(WIDTH); 
end architecture RCA; 

-- Carry Select Adder 
architecture CSA of ADDER is 
    component ADDER is 
    generic(WIDTH : positive); 
    port(CIN : in std_logic; 
      A : in std_logic_vector(WIDTH-1 downto 0); 
      B : in std_logic_vector(WIDTH-1 downto 0); 
      F : out std_logic_vector(WIDTH-1 downto 0); 
      COUT : out std_logic); 
    end component ADDER; 
    signal F0, F1  : std_logic_vector(WIDTH-1 downto 0); 
    signal COUT0, COUT1 : std_logic; 
begin 
    ADD0: ADDER generic map(WIDTH => WIDTH) 
    port map ( 
      CIN => '0' , 
      A => A , 
      B => B , 
      F => F0 , 
      COUT => COUT0); 
    ADD1: ADDER generic map(WIDTH => WIDTH) 
    port map ( 
      CIN => '1' , 
      A => A , 
      B => B , 
      F => F1 , 
      COUT => COUT1); 
    COUT <= COUT1 when CIN = '1' else COUT0; 
    F <= F1 when CIN = '1' else F0; 
end architecture CSA; 

-- here's the configuration 
configuration CSAC of ADDER is 
    for CSA 
    for all: ADDER 
     use entity work.ADDER(RCA); 
    end for; 
    end for; 
end configuration CSAC; 

http://www.edaplayground.com/x/2Yu3