2015-02-18 70 views
0

你好,我想完成這件事VHDL-交換機正確的代碼

GDF File Image (點擊)

,我已經寫了這個代碼,是正確的嗎? 因爲我在MAX + PLUS II編譯器不顯示任何錯誤...

LIBRARY IEEE; 
USE IEE.STD_LOGIC_1164.ALL; 

ENTITY alarm IS PORT 
(ON/OFF,MOTION_SENSOR,.LIGHT_SENSOR,.SOUND_SENSOR,.CAMERA_SENSOR,.IP_SENSOR,.TEMPERATURE_SENSOR: IN STD_LOGIC; 
SENSOR_SIRINE,SENSOR_LIGHT:OUT STD_LOGIC); 
END alarm; 

ARCHITECTURE LEITOURGEIA OF alarm IS 
BEGIN 
if (ON/OFF='1' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then 
SENSOR_LIGHT<='1'; 
SENSOR_SIRINE<='1'; 

ELSE IF (ON/OFF='0' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then 
SENSOR_LIGHT<='1'; 
SENSOR_SIRINE<='0'; 

ELSE 
SENSOR_LIGHT<='0'; 
SENSOR_SIRINE<='0'; 

END IF 

END LEITOURGEIA; 
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你錯過了一個分號:

而這其中甚至更類似於參考電路。 ON/OFF不是VHDL中的合法標識符,也不是以句點開頭的標識符。 if語句不是併發語句。 – user1155120 2015-02-18 00:17:30

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不是合法標識符的含義?開/關是輸入 – 2015-02-18 00:19:09

+2

夥計,這不是VHDL。 – user1155120 2015-02-18 00:21:51

回答

1

這是你的代碼是什麼樣子的有效VHDL近似:

library ieee; 
use ieee.std_logic_1164.all; 

entity alarm is 
    port (
     on_off, motion_sensor, light_sensor, 
     sound_sensor, camera_sensor, ip_sensor, 
     temperature_sensor:   in std_logic; 
     sensor_sirine, sensor_light: out std_logic 
    ); 
end alarm; 

architecture leitourgeia of alarm is 
begin 
unlabelled: 
    process (on_off, motion_sensor, light_sensor, sound_sensor, 
      camera_sensor, ip_sensor, temperature_sensor) 
    begin 
     if on_off = '1' and 
      (motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or 
      camera_sensor = '1' or ip_sensor = '1' or temperature_sensor='1') then 
      sensor_light <= '1'; 
      sensor_sirine <= '1'; 
     elsif on_off = '0' and 
      (motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or 
      camera_sensor = '1' or ip_sensor = '1' or temperature_sensor = '1') then 
      sensor_light <= '1'; 
      sensor_sirine <= '0'; 
     else 
      sensor_light <= '0'; 
      sensor_sirine <= '0'; 
     end if; 
    end process; 
end leitourgeia; 

我縮進它,固定一些拼寫錯誤,使有效的標識符,把if語句放在一個進程中,並使elsifelsif,加上擺脫兩組多餘的括號。

它現在分析,闡述和模擬。

所以做這種架構:

architecture foo of alarm is 
    signal alarm_light: std_logic; 
begin 
    alarm_light <= motion_sensor or sound_sensor or light_sensor or 
        camera_sensor or ip_sensor or temperature_sensor; 

    sensor_light <= alarm_light; 

    sensor_sirine <= '1' when alarm_light = '1' and on_off = '1' else 
        '0'; 
end architecture foo; 

哪個更類似於參考電路圖像。在`結束後if`

architecture fum of alarm is 
    signal alarm_light: std_logic; 
begin 
    alarm_light <= motion_sensor or sound_sensor or light_sensor or 
        camera_sensor or ip_sensor or temperature_sensor; 

    sensor_light <= alarm_light; 

    sensor_sirine <= on_off and alarm_light; 
end architecture fum; 
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非常感謝 – 2015-02-18 00:40:57

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以大寫形式輸入,輸出和語句(if,elseif)的名稱是否存在問題? – 2015-02-18 00:42:29

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不,這不是問題,常規標識符和保留字不區分大小寫; – user1155120 2015-02-18 00:43:36