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我在VHDL程序，從文件中讀取一行並應該根據該行的單個字符分配的信號值。我面臨的問題是我的FILE_OPEN語句似乎不工作。VHDL FILE_OPEN不返回正確的狀態
FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE);
的fstatus總是有OPEN_OK如果未初始化或者它被初始化爲值不會改變。該程序的完整代碼如下。
library IEEE;
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
--use ieee.std_logic_1164_additions.all
entity imem is -- instruction memory
port(a: in STD_LOGIC_VECTOR(5 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0));
end;
architecture behave of imem is
begin
process is
file mem_file: TEXT;
variable L, my_line: line;
variable L_ch : string(1 to 8);
variable ch, charac: character;
variable i, index, result: integer;
variable valid : boolean; -- to record whether a read is successful or not
variable fstatus: FILE_OPEN_STATUS;
type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
variable mem: ramtype;
begin
-- initialize memory from file
for i in 0 to 63 loop -- set all contents low
mem(i) := (others => '0');
end loop;
index := 0;
--fstatus := NAME_ERROR;
FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE);
report "Got status from file: '" & FILE_OPEN_STATUS'image(fstatus) & "'";
IF fstatus = OPEN_OK THEN
while not endfile(mem_file) loop
readline(mem_file, L);
report "Got line from file: '" & L.all & "'";
result := 0;
for i in 1 to 8 loop
read(L, ch, valid);
--write(my_line, string'(L_ch)); -- formatting
--writeline(output, my_line);
if (L'length = 0) then report "line empty " & integer'image(index)
severity error;
end if;
--ch := L_ch(i);
read(L, charac);
if '0' <= ch and ch <= '9' then
result := character'pos(ch) - character'pos('0');
elsif 'a' <= ch and ch <= 'f' then
result := character'pos(ch) - character'pos('a')+10;
else report "Format error on line " & integer'image(index) & character'image(ch) & character'image(charac) & boolean'image(valid) --& to_string(L_ch)
severity error;
end if;
mem(index)(35-i*4 downto 32-i*4) :=std_logic_vector(to_unsigned(result,4));
end loop;
index := index + 1;
end loop;
-- read memory
loop
rd <= mem(to_integer(unsigned(a)));
wait on a;
end loop;
file_close(mem_file);
end if;
wait;
end process;
end;
我正在使用Quartus Prime Lite進行合成。