我想實現K & R算法,用於計算256位向量的漢明重量。我寫我的代碼的VHDL爲:已超出非靜態循環限制
entity counter_loop is
Port (dataIn : in STD_LOGIC_VECTOR (255 downto 0);
dataOut : out STD_LOGIC_VECTOR (8 downto 0);
threshold : in STD_LOGIC_VECTOR (8 downto 0);
clk : in STD_LOGIC;
flag : out STD_LOGIC);
end counter_loop;
architecture Behavioral of counter_loop is
signal val : STD_LOGIC_VECTOR (255 downto 0) := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
begin
process (clk)
variable count : STD_LOGIC_VECTOR (8 downto 0):= "000000000";
begin
flag <= '0';
val <= dataIn;
--if(clk'event and clk = '1') then
while (val > 0) loop
count := count+1;
val <= (val and (val-1));
if (count > threshold) then
flag <= '1';
end if;
end loop;
dataOut <= count;
--end if;
end process;
end Behavioral;
但是,儘管採用Xilinx合成它,在錯誤出現的
53行:非靜態環超限
任何線索嗎?
P.S:53號線 - 而(值> 0)環
不要你的意思是「循環結束;」而不是「結束」;? – 2014-12-21 23:59:09
@LuísMarques:你是對的。謝謝。 – 2014-12-22 00:35:32