類型不匹配錯誤，如何解決這個

Question

這裏是我的一個簡單的ALU是加減

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
library IEEE; 
use IEEE.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 

entity alu is 
Port (A : in STD_LOGIC_VECTOR (15 downto 0); 
     B : in STD_LOGIC_VECTOR (15 downto 0); 
      funct: in STD_LOGIC; 
      op: in STD_LOGIC_VECTOR (1 downto 0); 
     Result : out STD_LOGIC_VECTOR (15 downto 0)); 
end alu; 

architecture Behavioral of alu is 
begin 

process (op, funct) 
begin 
    case op is 
    when "00" => Result <= A+B; 
    when "01" => Result <= A-B; 
    when others => case funct is 
         when "0" => Result <= A+B; 
         when "1" => Result <= A-B; 
         when others => null; 
    end case; 
`end case; 
end process; 
end Behavioral; 

我收到以下錯誤

ERROR:HDLParsers:800 - "E:/Xilinx Projects/alu/alu.vhd" Line 51. Type of funct is  incompatible with type of 0. 
ERROR:HDLParsers:800 - "E:/Xilinx Projects/alu/alu.vhd" Line 52. Type of funct is incompatible with type of 1. 
ERROR:HDLParsers:163 - "E:/Xilinx Projects/alu/alu.vhd" Line 55. Unexpected symbol read: `. 

代碼，我知道這事做類型不匹配的'功能'和'結果'，但我不知道如何解決它，任何想法？

Answer 1

此分析：

library ieee; 
use ieee.std_logic_1164.all; 
-- library ieee; -- successive library clause has no effect 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 

entity alu is 
    port ( 
     a:  in std_logic_vector (15 downto 0); 
     b:  in std_logic_vector (15 downto 0); 
     funct: in std_logic; 
     op:  in std_logic_vector (1 downto 0); 
     result: out std_logic_vector (15 downto 0) 
    ); 
end alu; 

architecture behavioral of alu is 
begin 

process (op, funct) 
begin 
    case op is 
     when "00" => 
      result <= a+b; 
     when "01" => 
      result <= a-b; 
     when others => 
      case funct is 
       when '0' => result <= a+b; -- "0" 
       when '1' => result <= a-b; -- "1" 
       when others => null; 
      end case; 
    end case; -- `end case; 
end process; 
end behavioral; 

類型STD_LOGIC具有使用字符文字枚舉和本身就是一個標量，沒有資格有一個字符串分配給funct。從std_logic_1164包聲明：

------------------------------------------------------------------- 
TYPE std_ulogic IS ('U', -- Uninitialized 
        'X', -- Forcing Unknown 
        '0', -- Forcing 0 
        '1', -- Forcing 1 
        'Z', -- High Impedance 
        'W', -- Weak  Unknown 
        'L', -- Weak  0 
        'H', -- Weak  1 
        '-' -- Don't care 
        ); 
------------------------------------------------------------------- 

和：

------------------------------------------------------------------- 
SUBTYPE std_logic IS resolved std_ulogic; 

------------------------------------------------------------------- 

正如你的問題的評論中提及的重音字符不應該在第二end case;的前面。