我在VHDL中有此代碼。當我嘗試編譯它時 - 它說「門控時鐘net clock_en是由一個組合引腳產生的。」有沒有人有一個想法如何擺脫這個警告? 我在互聯網上搜索過,找不到解決方案。看起來門控時鐘有時甚至是有用的,但是在設計硬件時它是一個警告。門控時鐘的原因
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ledc8x8 is
port(
SMCLK: in std_logic;
RESET: in std_logic;
ROW: out std_logic_vector(0 to 7);
LED: out std_logic_vector(0 to 7)
);
end ledc8x8;
architecture behavioral of ledc8x8 is
signal count: std_logic_vector(7 downto 0) := (others => '0'); -- hlavni citac
signal row_count: std_logic_vector(7 downto 0) := "10000000"; -- prepinac radku
signal clock_en: std_logic; -- CE
signal output_logic: std_logic_vector(7 downto 0); -- "vystup"
begin
process(count, SMCLK, RESET, clock_en)
begin
if RESET = '1' then
count <= (others => '0');
elsif SMCLK = '1' and SMCLK'event then
count <= count + 1;
end if;
if count="11111110" then
clock_en <= '1'; else
clock_en <= '0';
end if ;
end process;
process(clock_en, RESET)
begin
if RESET = '1' then
row_count <= "10000000";
elsif clock_en = '1' and clock_en'event then
row_count <= row_count(0) & row_count(7 downto 1);
end if;
end process;
process(row_count)
begin
case row_count is
when "00000001" => output_logic <= "11110110";
-- more switch options
end case;
end process;
ROW <= row_count;
LED <= output_logic;
end behavioral;
感謝您的幫助。感謝。 – Croolman 2014-11-05 18:29:56