我有這樣的VHDL代碼哪些錯誤與此VHDL代碼
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity addDecoder is
port(addrInput : in real;
ROM_sel_n, RAM_sel_n, PIO_sel_n, SIO_sel_n, INT_sel_n : out bit);
end addDecoder;
architecture Behavioral of addDecoder is
begin
AddSelect : process(addrInput) is
begin
if(addrInput <= X'3FFF') then
ROM_sel_n <= '1';
elsif(addrInput > X'3FFF' and addrInput <= X'5FFF') then
RAM_sel_n <= '1';
elsif(addrInput > X'5FFF' and addrInput <= X'8FFF') then
PIO_sel_n <= '1';
elsif(addrInput > X'8FFF' and addrInput <= X'9FFF') then
SIO_sel_n <= '1';
elsif(addrInput > X'9FFF' and addrInput <= X'FFFF') then
INT_sel_n <= '1';
end process AddSelect;
end Behavioral;
有什麼不妥的地方。我在比較十六進制值時遇到錯誤。我沒有正確地做這件事嗎?錯誤是:解析錯誤,意外的INTEGER_LITERAL,期望OPENPAR或IDENTIFIER
檢查addrInput的數據類型;我懷疑你打算使用std_logic_vector,而不是真實的。而且,地址解碼通過屏蔽比特來實現,而不是整數比較。 – 2011-02-08 03:07:14
謝謝我會研究掩蔽位。 – JC2 2011-02-08 03:38:37