MAX 10 ADC with VHDL/Quartus Prime Lite代碼優化

首先，我不得不說我是VHDL的補充初學者，所以如果它提出了一個真正愚蠢的問題，我想提前致歉。我試圖讓ADC軟IP工作。我只想使用ADC，所以沒有FIFO或其他任何東西。因此我使用qsys文件生成IP核並將其包含到我的項目中。我還用預分頻器激活了通道8。我試圖讀取連接到通道8的可變電阻的值，並打印出LED的5個最高有效位。 case語句應創建激活adc所需的模式，如MAX 10 ADC指南中給出的。MAX 10 ADC with VHDL/Quartus Prime Lite代碼優化

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 



entity main is 
    port (CLK_50 : in std_logic; 
      LEDR : out std_logic_vector(4 downto 0)); 
end; 


architecture behave of main is 

    signal Cnt : integer := 0; 
    signal pCnt : integer := 0; 

    signal lock : std_logic; 
    signal CLK_10 : std_logic; 
    signal CLK_1 : std_logic; 
    signal set : std_logic ; 

    signal RESET : std_logic ; 

    signal CMDVal : std_logic; 
    signal CMDCH : std_logic_vector (4 downto 0); 
    signal CMDSOP : std_logic; 
    signal CMDEOP : std_logic; 
    signal CMDRDY : std_logic; 
    signal RESVal : std_logic; 
    signal RESCH : std_logic_vector (4 downto 0); 
    signal RESData : std_logic_vector (11 downto 0); 
    signal RESSOP : std_logic; 
    signal RESEOP : std_logic; 

    component myadc is 
     port (
      clock_clk    : in std_logic      := 'X';    -- clk 
      reset_sink_reset_n  : in std_logic      := 'X';    -- reset_n 
      adc_pll_clock_clk  : in std_logic      := 'X';    -- clk 
      adc_pll_locked_export : in std_logic      := 'X';    -- export 
      command_valid   : in std_logic      := 'X';    -- valid 
      command_channel  : in std_logic_vector(4 downto 0) := (others => 'X'); -- channel 
      command_startofpacket : in std_logic      := 'X';    -- startofpacket 
      command_endofpacket : in std_logic      := 'X';    -- endofpacket 
      command_ready   : out std_logic;          -- ready 
      response_valid   : out std_logic;          -- valid 
      response_channel  : out std_logic_vector(4 downto 0);      -- channel 
      response_data   : out std_logic_vector(11 downto 0);     -- data 
      response_startofpacket : out std_logic;          -- startofpacket 
      response_endofpacket : out std_logic           -- endofpacket 
     ); 
    end component myadc; 

begin 

    CMDCH <= "01000"; 
    RESET <= '0'; 
    set <= '1'; 

    mPLL : entity work.pll 
     port map(
     areset => set, 
     inclk0 => CLK_50, 
     c0 => CLK_10, 
     c1 => CLK_1, 
     locked => lock 
    ); 


    mADC : component myadc 
     port map (
      clock_clk    => CLK_50,     --   clock.clk 
      reset_sink_reset_n  => RESET,      --  reset_sink.reset_n 
      adc_pll_clock_clk  => CLK_10,     -- adc_pll_clock.clk 
      adc_pll_locked_export => lock,       -- adc_pll_locked.export 
      command_valid   => CMDVal,     --  command.valid 
      command_channel  => CMDCH,     --    .channel 
      command_startofpacket => CMDSOP,     --    .startofpacket 
      command_endofpacket => CMDEOP,     --    .endofpacket 
      command_ready   => CMDRDY,     --    .ready 
      response_valid   => RESVal,     --  response.valid 
      response_channel  => RESCH,      --    .channel 
      response_data   => RESData,    --    .data 
      response_startofpacket => RESSOP,     --    .startofpacket 
      response_endofpacket => RESEOP     --    .endofpacket 
     ); 

process 
begin 

    wait until rising_edge(CLK_50); 

    pCnt <= pCnt + 1; 

    case pCnt is 
     when 1 => CMDSOP <= '1'; 
        CMDVal <= '1'; 
     when 114 => CMDRDY <= '1'; 
     when 115 => CMDSOP <= '0'; 
         CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 214 => CMDRDY <= '1'; 
     when 215 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 314 => CMDRDY <= '1'; 
     when 315 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 414 => CMDRDY <= '1'; 
     when 415 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 514 => CMDRDY <= '1'; 
     when 515 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 614 => CMDRDY <= '1'; 
     when 615 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 714 => CMDRDY <= '1'; 
     when 715 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 814 => CMDRDY <= '1'; 
     when 815 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 914 => CMDRDY <= '1'; 
     when 915 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7); 
     when 1014 => CMDRDY <= '1'; 
     when 1015 => CMDRDY <= '0'; 
         LEDR <= RESData(11 downto 7);  
     when 1114 => CMDRDY <= '1'; 
     when 1115 => CMDRDY <= '0'; 
         CMDEOP <= '1'; 
     when 1116 => CMDEOP <= '0'; 
         CMDVal <= '0'; 


     when 2000 => pCnt <= 0; 
     when others => Cnt <= pCnt ; 
    end case; 
end process; 

end;

但是編譯Quartus時總是會刪除我所有的代碼。所以最後它將LED拉到GND，既不使用ADC也不使用PLL。如果任何人有一個想法，我會非常感謝，如果你能告訴我什麼exaclty即時做錯了。

此致敬禮。

編輯：我沒有足夠清楚地描述我的問題。它確實合成正確，但它認爲pll不是必需的，因此將其刪除，使adc ip核心沒有時鐘，因此也將其刪除。的錯誤是：

Warning (14284): Synthesized away the following node(s): 
    Warning (14285): Synthesized away the following RAM node(s): 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[0]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[1]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[2]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[3]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[4]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[5]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[6]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[7]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[8]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[9]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[10]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[11]" 
Warning (14284): Synthesized away the following node(s): 
    Warning (14285): Synthesized away the following RAM node(s): 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[0]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[1]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[2]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[3]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[4]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[5]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[6]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[7]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[8]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[9]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[10]" 
     Warning (14320): Synthesized away node "madc:myadc|madc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|altera_modular_adc_control_fsm:u_control_fsm|altera_modular_adc_control_avrg_fifo:ts_avrg_fifo|scfifo:scfifo_component|scfifo_ds61:auto_generated|a_dpfifo_3o41:dpfifo|altsyncram_rqn1:FIFOram|q_b[11]" 
Warning (14284): Synthesized away the following node(s): 
    Warning (14285): Synthesized away the following PLL node(s): 
     Warning (14320): Synthesized away node "mpll:myPLL|altpll:altpll_component|mpll_altpll:auto_generated|wire_pll1_clk[0]"

來源

2017-02-20 nuclear

當您的邏輯在優化期間被吃掉並且您的輸出連接到導軌時，它通常是邏輯設計錯誤或工具使用錯誤的標誌。在這種情況下，集中在用於驅動LEDR值的myadc的ResData上。除了myadc可能存在的邏輯問題之外，它還可以被解開，導致ResData不被驅動，整個設計的其餘部分被吃掉（LEDR是唯一的輸出）。您需要在綜合期間檢查控制檯輸出（或日誌）是否有警告和錯誤。 – user1155120

是的，我意識到問題是輸出不被驅動，所以我試圖將adc的數據保存在一個單獨的std_logic_vector中，並在每個時鐘週期驅動輸出，但是這並沒有改變問題。缺點是我不知道如何改變adc邏輯內的任何東西，因爲它的altera ip核心。我只能通過樣本存儲找到adc控件的教程。據我瞭解altera文件驅動adc的邏輯應該是正確的，但可悲的是我不能確認它。 – nuclear

你的讀者似乎不可能窺探黑匣子，並告訴你什麼是錯的，而不會被同樣的咬傷。您似乎在生成過程中正在處理IP內核配置。你說過你沒有使用FIFO，在myadc組件聲明中有一個PLL。 – user1155120

在VHDL（基本上在所有的硬件描述語言），你要記住，你的代碼必須synthetizable：它來形容你的可編程組件可用的硬件組件。在你的過程中情況並非如此。

以下行：wait until rising_edge(CLK_50);由於wait語句而無法合成。

要創建你需要這個順序的過程：

my_seq_proc : process (clk, rst) 
begin 
    if (rst = '1') then 
     ... -- reset your signals 
    elsif (rising_edge(clk)) then 
     ... -- what you need to do 
    end if; 
end process;

請注意，您不一定要使用一個復位信號。此外，請注意，您需要在時鐘（clk_50）和可能的復位信號的過程聲明(clk, rst)中使用靈敏度列表。

我還沒有檢查是否有另一個錯誤。你應該嘗試先做到這一點。

來源

2017-02-20 15:54:06

推薦的編碼風格與支持的推理寄存器風格之間存在差異。建議的樣式可在第1卷設計和綜合手冊中找到。支持的樣式位於撤消的IEEE Std 1076.6-2004 IEEE標準VHDL寄存器傳輸級別（RTL）綜合中。在這種特殊情況下，6.1.3.2使用單個等待語句的邊緣敏感存儲與OP的使用相匹配。預計Altera的綜合工具將符合撤回的IEEE標準。 – user1155120

據我所知等到rising_edge（clk）是一個完全有效的選項，只要你不想重置。反正它沒有問題之前合成過。然而，雖然syhetizing由於某種原因刪除了pll，所以當然所有的邏輯根本不起作用。但我也改變了你如何推薦它，但它仍然無法正常工作。 – nuclear

不知道「等到」是否被Altera支持進行合成。那我很抱歉。 –

MAX 10 ADC with VHDL/Quartus Prime Lite代碼優化

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