有人可以幫我找到我陷入一個循環VHDL

Question

我對項目使用有限狀態機，但是當我去模擬它時，我發送shift_button爲'1'時出現迭代錯誤。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity LFSR_FSM is 
    Port (load_button : in STD_LOGIC; 
      input : in STD_LOGIC_VECTOR (7 downto 0); 
      key : inout STD_LOGIC_VECTOR (7 downto 0); 
      shift_button : in STD_LOGIC; 
       Clock : in STD_LOGIC); 
end LFSR_FSM; 
architecture Behavioral of LFSR_FSM is 

type State_type is (Prime,Shift,Memory); 
signal Sreg, Snext: State_type; 
signal mem,shifted_output : STD_LOGIC_VECTOR (7 downto 0); 
signal seven,six,five,four,three,two,one,zero : STD_LOGIC; 
begin 
    process (Sreg,input,load_button,shift_button) 
     begin 
     case Sreg is 
      when Memory => if shift_button = '1' then Snext <= Shift; 
           elsif load_button = '1' then Snext <= Prime; 
           else Snext <= Memory; 
          end if; 

      when Shift => Snext <= Memory; 


      when Prime => if load_button = '1' then Snext <= Prime; 
          else Snext <= Memory; 
          end if; 

      when others => Snext <= Memory; 
     end case; 
end process; 
process (Clock) 
    begin 
    if Clock'event and Clock = '1' then 
    Sreg <= Snext; 
    end if; 
end process; 

--key <= output ; 
with Sreg select 
key <= input when Prime, 
     shifted_output when Shift, 
     mem when others; 
mem <= key; 
shifted_output<=(zero,seven,six,five,four,three,two,one); 
    seven <= mem(7); 
    six <= mem(6); 
    five <= mem(0) xor mem(6); 
    four <= mem(0) xor mem(5); 
    three <= mem(0) xor mem(4); 
    two <= mem(2); 
    one <= mem(1); 
    zero <= mem(0); 
end Behavioral; 

這是我在我的模擬結束後20納秒 load_button < = '1'， '0' 後30納秒， '1' 後40納秒， '0' 後50納秒;
輸入< = 10納秒後的「00110100」; shift_button < = 60 ns後的'1'，70 ns後的'0'

Answer 1

當FSM進入Shift狀態時，您有一個涉及key -> mem -> (numbers) -> shifted_output -> key的組合循環。這會導致您的模擬器迭代delta循環，直到達到極限。我建議通過將with-select移入鍾控過程來註冊關鍵信號。如果使用VHDL-2008，則可以保持不變，或者轉換爲具有較早標準的案例聲明。