我有一個VHDL代碼用於讀取和寫入8位數據到每個地址8位的RAM,但我需要更改該代碼用於以每個地址8位的數據讀/寫16位數據到RAM。 可以做些什麼改變?VHDL:如何讀取/寫入RAM中的16位數據,每個地址8位
初始代碼我有是:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM is
port(address: in std_logic_vector(0 to 15);
datain: in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(7 downto 0);
WE, CS, OE: in std_logic);
end entity RAM;
architecture behavior6 of RAM is
type RAM_type is array (0 to 2**16) of std_logic_vector(7 downto 0);
signal RAM1: RAM_type;
begin
process (address, CS, WE, OE)
begin
dataout <= (others => 'Z'); --chip is not selected (this is the first row of the T.T)
if (CS = '0')
then
if WE= '0' then --we want to write
RAM1(to_integer(unsigned(address))) <= datain;
end if;
if WE= '1' and OE= '0'
then--we want to read
dataout <= RAM1(to_integer(unsigned(address)));
else
dataout <= (others => 'Z');
end if;
end if;
end process;
end behavior6;
讀/寫數據。或者將這些實體中的2個放入新的實體中。 –