Verilog測試模擬誤差

Question

module stimulus; 
reg [511:0]FROM_LS; 
reg CLOCK; 
reg [2:0]HMIC_CTRL; 
reg [20:0]BRANCH_CTRL; 
reg [63:0]TO_IF_ID; 
reg FLUSH_CTRL; 
reg [20:0]TO_LS; 

inst_line_buf ILB(FLUSH_CTRL,TO_LS,FROM_LS,CLOCK,HMIC_CTRL,BRANCH_CTRL,TO_IF_ID); 

// setup clock 
initial 
begin 

    #10 CLOCK = ~CLOCK; 

// apply stimulus 

    FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01; 
    FROM_LS[479:448]=32'b000_11000_00100_01111_11111_00011_1000; 

    HMIC_CTRL[2:0]=3'b000; 
    BRANCH_CTRL[20:0]=20'b00000_00000_00000_00000; 
    #2 $display("FLUSH CONTROL=%b, TO_LS= %b",FLUSH_CTRL,TO_LS); 
end 

endmodule

，我發現了以下錯誤：

# Loading work.inst_line_buf 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (512 or 512) does not match connection size (1) for port 'from_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(1). 
#   Region: /stimulus/ILB 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'clk'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(2). 
#   Region: /stimulus/ILB 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (3 or 3) does not match connection size (512) for port 'hmic_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(3). 
#   Region: /stimulus/ILB 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (1) for port 'branch_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(4). 
#   Region: /stimulus/ILB 
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_if_id'". 
#   Region: /stimulus/ILB 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (64 or 64) does not match connection size (3) for port 'to_if_id'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(5). 
#   Region: /stimulus/ILB 
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'flush_ctrl'". 
#   Region: /stimulus/ILB 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (21) for port 'flush_ctrl'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(6). 
#   Region: /stimulus/ILB 
# ** Error: (vsim-3053) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): Illegal output or inout port connection for "port 'to_LS'". 
#   Region: /stimulus/ILB 
# ** Warning: (vsim-3015) C:/Modeltech_pe_edu_10.0a/examples/stimulus_ilb.v(10): [PCDPC] - Port size (21 or 21) does not match connection size (64) for port 'to_LS'. The port definition is at: C:/Modeltech_pe_edu_10.0a/examples/inst_line_buf.v(7). 
#   Region: /stimulus/ILB 
# Error loading design 

Answer 1

除非你告訴我們完整的錯誤消息，並且vsim命令行和一些相關的Verilog代碼，我們所能提供的只是向Google提出您的錯誤消息的建議。

例如，從modelsim_FAQ：

的ModelSim仿真選項沒有 設置正確（項目設置> 的ModelSim>選項）進行以下 變化：在項目右鍵單擊模擬 標籤流程窗口或 選擇項目>設置>模擬 測試臺模塊名稱：指定您的 測試臺模塊名稱頂層 實例名稱在測試臺中： DUT的實例名稱請參閱 下面的截圖爲例。

更新：現在您已經添加了一些代碼，ILB看起來很可疑。您使用第一個作爲inst_line_buf模塊的實例名稱，然後在initial塊中再次使用它，看起來像函數或任務調用。我的猜測是，你想要的initial塊外，但與端口連接：

inst_line_buf ILB (FROM_LS,CLOCK,HMIC_CTRL,TO_IF_ID,FLUSH_CTRL,TO_LS);