如何測試一個VHDL文件

Question

我已經用VHDL做了一個雙端口寄存器庫，我想測試它以確保它能正常工作。我會如何去做這件事？我知道我想做什麼（將寄存器2設置爲常量，在測試程序中讀出它，寫入寄存器3並將其讀回並查看我是否具有相同的結果）。我只是VHDL的新手，所以我不知道是否有控制檯，測試程序是如何構建的，或者如何實例化寄存器文件，甚至不知道如何編譯它（I'迄今爲止一直使用quartus）。

這是我的寄存器文件：

所有的

use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 

-- Register File 

entity RF is 

port(
    signal clk, we: in std_logic; 
    signal ImmediateValue : in std_logic_vector(15 downto 0); 
    signal RegisterSelectA, RegisterSelectB : in integer range 0 to 15; 

    signal AOut, BOut : out std_logic_vector(15 downto 0) 
); 

end RF 

architecture behavior of RF is 

    array std_logic_vector_field is array(15 downto 0) of std_logic_vector(15 downto 0); 
    variable registers : std_logic_vector(15 downto 0); 

    process (clk, we, RegisterSelectA, RegisterSelectB, ImmediateValue) 
     wait until clk'event and clk = '1'; 
     registers(RegisterSelectA) := ImmediateValue when we = '1'; 
     AOut <= registers(RegisterSelectA); 
     BOut <= registers(RegisterSelectB); 
    end process; 

end behavior; 

Answer 1

首先，如果你是新的VHDL設計，你可能是最好關閉與網絡上的教程開始，或抓住一本書像"The Designer's Guide to VHDL"。

無論如何，就像軟件設計一樣，爲了測試VHDL設計，您必須編寫一些測試代碼。在硬件設計中，通常這些測試是單元測試，但通常稱爲"testbenches"。

對於你給的設計，你需要創建這樣的事情：

library ieee.std_logic_1164.all; 
library ieee.numeric_std.all; 

entity test_RF is 
end entity; 

architecture test of test_RF is 
    signal clk, we: std_logic; 
    signal ImmediateValue : std_logic_vector(15 downto 0); 
    signal RegisterSelectA, RegisterSelectB : integer range 0 to 15; 
    signal AOut, BOut : std_logic_vector(15 downto 0) 
begin 

    -- Instantiate the design under test 
    u_RF : entity work.RF 
    port map (
    clk => clk, 
    we => we, 
    ImmediateValue => ImmediateValue, 
    RegisterSelectA => RegisterSelectA, 
    RegisterSelectB => RegisterSelectB, 
    AOut => AOut, 
    BOut => BOut 
); 

    -- create a clock 
    process is 
    begin 
    clk <= '0'; 
    loop 
     wait for 10 ns; 
     clk <= not clk; 
    end loop; 
    end process; 

    -- create one or more processes to drive the inputs and read the outputs 
    process is 
    begin 
    wait until rising_edge(clk); 
    -- do stuff 
    -- use assert to check things 
    -- etc 
    end process; 

end architecture;