錯誤與VHDL腳本語法

Question

我有這樣的代碼我想要做的LSFR，但我有幾個問題，包括：

ERROR:HDLParsers:3010 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 18. Entity LFSR does not exist.
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 19. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 19. std_logic_vector: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 20. Undefined symbol 'std_logic'.
ERROR:HDLParsers:1209 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 20. std_logic: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Users/user/Documents/tp_vhdl/median_LSFR/LSFR.vhd" Line 24. Undefined symbol 's_xor1'.

代碼：

library ieee; 
use ieee.std_logic_1164.all; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 


entity LSFR is port (
    clk : in std_logic; 
    reset,en : in std_logic; 
    de1,de2 : out std_logic_vector(2 downto 0) 
    ); 
end LSFR; 


architecture arch of LFSR is 
signal etatpresent, etatfutur : std_logic_vector(16 downto 1); 
signal s_xor1, s_xor2, s_xor3 : std_logic; 
begin 

-- Calcul intermediaire des ou exclusifs 
s_xor1 <= etatpresent(15) xor etatpresent(1); 
s_xor2 <= etatpresent(14) xor etatpresent(1); 
s_xor3 <= etatpresent(12) xor etatpresent(1); 

-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs 

process(etatpresent) begin 

etatfutur(16) <= etatpresent(1); 
etatfutur(1) <= etatpresent(2); 
etatfutur (2) <= etatpresent(3); 
etatfutur (3) <= etatpresent(4); 
etatfutur (4) <= etatpresent(5); 
etatfutur (5) <= etatpresent(6); 
etatfutur (6) <= etatpresent(7); 
etatfutur (7) <= etatpresent(8); 
etatfutur (8) <= etatpresent(9); 
etatfutur (9) <= etatpresent(10); 
etatfutur (10) <= etatpresent(11); 
etatfutur (11) <= s_xor3; 
s_xor3 <= etatpresent(12); 
etatfutur (12) <= etatpresent(13); 
etatfutur (13) <= s_xor2; 
s_xor2 <= etatpresent(14); 
etatfutur (14) <= s_xor1; 
s_xor1 <= etatpresent(15); 
etatfutur (15) <= etatpresent(16); 

end process; 

process(reset) begin 
       if (reset = '1') then 
        etatfutur <="0000000000000001"; 
       end if ; 
end process; 


-- cablage des deux sorties 
de1(2 downto 0) <= etatpresent(16 downto 14); 
de2 (2 downto 0) <= etatpresent(3 downto 1); 
end arch; 

Answer 1

儘管您沒有識別行號，但它們不匹配，第一個錯誤是LFSR不像Martin Zobel所表明的那樣是架構拱的聲明實體。它似乎是實體聲明中拼寫錯誤的實體名稱，它是結束語句。

如果不借助因特網搜索來識別產生錯誤消息的VHDL工具，它看起來並不完全符合標準，Maria可能會在她的評論中看到某些東西，並且認識到了錯誤消息的來源。

通常情況下，上下文子句中的重複庫名將被忽略，同樣的內部聲明區中使用子句中的複製聲明也會被忽略。

理順實體名稱和上下文條款（除去多餘的元素）：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity LFSR is -- was LSFR is port (
    port (
     clk:  in std_logic; 
     reset, en: in std_logic; 
     de1, de2: out std_logic_vector(2 downto 0) 
    ); 
end entity LFSR; -- was end LSFR; 

architecture arch of LFSR is -- Line 16, LFSR doesn't match LSFR 
    signal etatpresent, etatfutur: std_logic_vector(16 downto 1); 
    signal s_xor1, s_xor2, s_xor3: std_logic; 
begin 

-- Calcul intermediaire des ou exclusifs 
    s_xor1 <= etatpresent(15) xor etatpresent(1); 
    s_xor2 <= etatpresent(14) xor etatpresent(1); 
    s_xor3 <= etatpresent(12) xor etatpresent(1); 

-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs 

    process (etatpresent) 
    begin 
     etatfutur(16) <= etatpresent(1); 
     etatfutur(1) <= etatpresent(2); 
     etatfutur (2) <= etatpresent(3); 
     etatfutur (3) <= etatpresent(4); 
     etatfutur (4) <= etatpresent(5); 
     etatfutur (5) <= etatpresent(6); 
     etatfutur (6) <= etatpresent(7); 
     etatfutur (7) <= etatpresent(8); 
     etatfutur (8) <= etatpresent(9); 
     etatfutur (9) <= etatpresent(10); 
     etatfutur (10) <= etatpresent(11); 
     etatfutur (11) <= s_xor3; 
     s_xor3 <= etatpresent(12); 
     etatfutur (12) <= etatpresent(13); 
     etatfutur (13) <= s_xor2; 
     s_xor2 <= etatpresent(14); 
     etatfutur (14) <= s_xor1; 
     s_xor1 <= etatpresent(15); 
     etatfutur (15) <= etatpresent(16); 
    end process; 

    process (reset, clk) -- added clock to sensitivity list 
    begin 
     if reset = '1' then 
      etatpresent <= "0000000000000001"; -- was etatfutur 
     elsif rising_edge(clk) and en = '1' then 
      etatpresent <= etatfutur; 
     end if; 
    end process; 

-- cablage des deux sorties 
    de1(2 downto 0) <= etatpresent(16 downto 14); 
    de2 (2 downto 0) <= etatpresent(3 downto 1); 

end architecture arch; 

爲我們提供了一些分析。注意我還將clk添加到進程敏感性列表中，更正了重置並添加了etatpresent寄存器。

那麼它工作？我們可以通過創建一個小的測試平臺和仿真發現：

library ieee; 
use ieee.std_logic_1164.all; 

entity lfsr_tb is 
end entity; 

architecture fum of lfsr_tb is 
    signal clk:  std_logic := '0'; 
    signal reset: std_logic; 
    signal en:  std_logic; 
    signal de1:  std_logic_vector (2 downto 0); 
    signal de2:  std_logic_vector (2 downto 0); 
begin 

DUT: 
    entity work.lfsr 
     port map (
      clk => clk, 
      reset => reset, 
      en => en, 
      de1 => de1, 
      de2 => de2 
     ); 
CLOCK: 
    process 
    begin 
     wait for 10 ns; 
     clk <= not clk; 
     if now > 450 ns then 
      wait; 
     end if; 
    end process; 
STIMULI: 
    process 
    begin 
     wait for 11 ns; 
     reset <= '1'; 
     en <= '0'; 
     wait for 20 ns; 
     reset <= '0'; 
     wait for 20 ns; 
     en <= '1'; 
     wait for 100 ns; 
     en <= '0'; 
     wait for 40 ns; 
     en <= '1'; 
     wait; 
    end process; 
end architecture; 

和仿真，讓我們的東西，看起來並不好：

到底發生了什麼？

仔細看看lfsr中未標記的第一個進程，顯示s_xor1，s_xor_2和s_xor3存在重複的驅動程序，以及這三個缺失的敏感列表（它們顯示在右側表達式中的作業）。

而不必你實現，我們可以簡單的添加缺少的靈敏度列表項的LFSR算法參考，並註釋掉驅動程序：

-- Calcul de l'état futur en fonction de l'état présent et des ou exclusifs 

    process (etatpresent, s_xor1, s_xor2, s_xor3) 
    begin 
     etatfutur(16) <= etatpresent(1); 
     etatfutur(1) <= etatpresent(2); 
     etatfutur (2) <= etatpresent(3); 
     etatfutur (3) <= etatpresent(4); 
     etatfutur (4) <= etatpresent(5); 
     etatfutur (5) <= etatpresent(6); 
     etatfutur (6) <= etatpresent(7); 
     etatfutur (7) <= etatpresent(8); 
     etatfutur (8) <= etatpresent(9); 
     etatfutur (9) <= etatpresent(10); 
     etatfutur (10) <= etatpresent(11); 
     etatfutur (11) <= s_xor3; 
     -- s_xor3 <= etatpresent(12); 
     etatfutur (12) <= etatpresent(13); 
     etatfutur (13) <= s_xor2; 
     -- s_xor2 <= etatpresent(14); 
     etatfutur (14) <= s_xor1; 
     -- s_xor1 <= etatpresent(15); 
     etatfutur (15) <= etatpresent(16); 
    end process; 

這給了我們一個無差錯的波形：

您需要根據算法的規範驗證LFSR操作。

請注意如何使兩個時鐘無效工作。

Answer 2

你拼寫LFSR錯的實體。 （「LSFR」）