2014-09-21 859 views
-1

我想調試我的代碼如下所示。我對SystemVerilog相當陌生,希望我能從中學習到。讓我知道任何建議。如何解決「錯誤 - [ICPSD]驅動程序的無效組合」?

**我收到的錯誤是:

Error-[ICPSD] Invalid combination of drivers 
    Variable "Q" is driven by an invalid combination of structural and 
    procedural drivers. Variables driven by a structural driver cannot have any 
    other drivers. 
    "divide.v", 13: logic [7:0] Q; 
    "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R); 
    "divide.v", 23: Q = 8'b0; 

    Error-[ICPSD] Invalid combination of drivers 
    Variable "R" is driven by an invalid combination of structural and 
    procedural drivers. Variables driven by a structural driver cannot have any 
    other drivers. 
    "divide.v", 13: logic [7:0] R; 
    "divide.v", 16: divide8bit testcase1(x, y, clk, Q, R); 
    "divide.v", 24: R = y; 

**我的SystemVerilog代碼是:

module divide8bit(
    input logic [7:0] x,y, 
    input logic clk, 
    output logic [7:0] Q,R); 

    always_ff @(posedge clk) 
    begin 
     R <= R-x; 
     Q <= Q + 8'd1; 
    end 
endmodule 

module test1; 

    logic [7:0] x,y,Q,R; 
    logic clk; 

    divide8bit testcase1 (x,y,clk,Q,R); 

    initial 
    begin 
      x = 8'd2; 
      y = 8'd8; 
      Q = 8'd0; 
      R = y; 
      clk = 1'd0; 
      while(x <= R) 
       begin 
        #5 clk = ~clk; 
       end 
      #5 $finish; 
     end 
endmodule 
+0

當從DUT分離測試時,我發現問題更具可讀性。較小的獨特代碼塊我發現更容易解析和理解層次結構,這對於未來的問題可能值得考慮。 – Morgan 2014-09-22 09:09:04

+0

謝謝你的洞察力。我現在將他們分開! – codewarrior453 2014-09-23 12:13:54

回答

1

Same problem這裏:你在裏面module test1分配給QR。同時module testcase1也在嘗試分配到QR。不要分配給Q和R test1

+0

你將如何去開始分配它們,並推遲總是。這是我唯一的問題。我一直在這個問題上待了好幾個小時。關於在始終循環中進行所有初始化的事情是,它會重複,我只需要它們從Q = 0開始,R = Y開始一次。 – codewarrior453 2014-09-21 05:18:10

+1

您正在實現Q和R作爲一個觸發器,可以使用復位信號進行初始化。使用異步重置的翻牌:http://www.asic-world.com/examples/verilog/d_ff.html – Ari 2014-09-21 05:21:07

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