這是激勵文件:如何在RAM中的數據存儲在VERILOG
module final_stim;
reg [7:0] in,in_data;
reg clk,rst_n,rd,wr,rd_data,wr_data;
wire [7:0] out,out_wr;
wire[7:0] d;
integer i;
reg kld,f;
reg [127:0]key;
wire [127:0] key_expand;
wire [7:0]out_data;
reg [7:0] k;
//wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [7:0] out_data1;
**//key_expand is da output which is giving 10 streams of size 128 bits.**
assign k1=key_expand[127:120];
assign k2=key_expand[119:112];
assign k3=key_expand[111:104];
assign k4=key_expand[103:96];
assign k5=key_expand[95:88];
assign k6=key_expand[87:80];
assign k7=key_expand[79:72];
assign k8=key_expand[71:64];
assign k9=key_expand[63:56];
assign k10=key_expand[55:48];
assign k11=key_expand[47:40];
assign k12=key_expand[39:32];
assign k13=key_expand[31:24];
assign k14=key_expand[23:16];
assign k15=key_expand[15:8];
assign k16=key_expand[7:0];
**// then the module of memory is instanciated.
//here k1 is sent as input.but i don know how to save the other values of k.
//i tried to use for loop but it dint help**
memory m1(clk,rst_n,rd, wr,k1,out_data1);
aes_sbox b(out,d);
initial
begin
clk=1'b1;
rst_n=1'b0;
#20
rst_n = 1;
wr_data=1'b1;
in=8'hd4;
#20
in=8'h27;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h11;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hae;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'he0;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hbf;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h98;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hf1;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hb8;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hb4;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h5d;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'he5;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h1e;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h41;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h52;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h30;
rd_data=1'b0;
wr_data=1'b1;
#20
wr_data=1'b0;
#380
rd_data=1'b1;
#320
rd_data = 1'b0;
///////////////
#10
kld = 1'b1;
key=128'h 2b7e151628aed2a6abf7158809cf4f3c;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b0;
#10
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
wr = 1'b0;
#20
rd = 1'b1;
end
always
#10 clk=~clk;
[email protected](posedge clk)
begin
#10000
$stop;
end
endmodule
我有在clk
每個posedge的128個比特的比特流,即,總共10比特的每個長度的128個比特流。
我想將128位數據流分成8位和8位,並且必須將它們存儲在寬度爲8位的RAM /存儲器中。
我通過將8位,8位分配給8位大小的導線來實現。這樣就有16根電線。我正在使用雙端口RAM。當我在刺激中調用內存模塊時,我不知道如何輸入,因爲我有16根不同的導線,名爲到k16
。
//Key expansion module to generate 128 bit streams(key reffered to as stream)
//This code generates 10 keys of 128 bits each at each positive edge of clock
module key_expansion(kld,clk,key,key_expand);
input kld,clk;
input [127:0] key;
wire [31:0] w0,w1,w2,w3;
output [127:0] key_expand;
reg [31:0] w[3:0];
wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [31:0] c0,c1,c2,c3;
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign w0 = w[0];
assign w1 = w[1];
assign w2 = w[2];
assign w3 = w[3];
always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out_rcon(rcon));
assign key_expand={w0,w1,w2,w3};
endmodule
//stimulus for key generation
module stim_key_exp;
reg kld ,clk;
reg [127:0]key;
wire [127:0] key_expand;
key_expansion x(kld,clk,key,key_expand);
initial
begin
clk=1'b1;
kld = 1'b1;
#20
kld=1'b0;
key=128'h 2b28ab097eaef7cf15d2154f16a6883c;
end
always
#5 clk=~clk;
[email protected](posedge clk)
begin
$monitor($time," key_expand=%h\n",key_expand);
#110
$stop;
end
endmodule
欲長度的每個鍵128位分割成8位的塊並且存儲它們。
需要考慮的一件事是在每個時鐘的正邊緣生成新的密鑰。
在生成下一個密鑰之前需要存儲一個密鑰。
請點擊「101010」按鈕對代碼進行格式化,並用點綴正確的英文寫入。 – Potatoswatter 2010-05-03 09:24:40
我已經編輯post.kindly幫助! – anum 2010-05-03 09:31:33
我已經發布了一個答案。請大寫每個句子的第一個字母,不要忽略單詞之間的空格,也不要縮寫任何內容。 – Potatoswatter 2010-05-03 09:39:13