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我在Verilog中編寫了加法器的門級代碼。加法器的輸出如下所示。正如你所看到的，總和和cout總是在z中。我不知道爲什麼。你能檢查我錯過了什麼嗎？謝謝你的時間。verilog模塊中加法器輸出的錯誤值
OUTPUT：
A = X，B = X，CIN = X，SUMM = Z，COUT = Z在時間= 0
A = 0，B = 0，CIN = 0，SUMM = Z，COUT = Z在時間= 10
A = 0，b = 1，CIN = 0，SUMM = Z，COUT = Z在時間= 20
A = 1，b = 0，CIN = 0，summ = z，時間= 30時的cout = z
a = 1，b = 1，cin = 0，summ = z，cout = z在時間= 40
A = 0，B = 0，CIN = 1，SUMM = Z，COUT = Z在時間= 50
A = 0，B = 1，CIN = 1，SUMM = Z ，COUT = Z在時間= 60
A = 1，b = 0，CIN = 1，SUMM = Z，COUT = Z在時間= 70
A = 1，b = 1，CIN = 1 ，summ = z，cout = z at時間= 80
module tb();
reg a, b, cin;
wire cout, summ;
FA_gatelevel gatelevel(.a(a), .b(b), .cin(cin), .summ(summ), .cout(cout));
initial begin
#10 a = 0; b = 0; cin = 0;
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
end
initial begin
$monitor("a = %0h, b = %0h, cin = %0h, sum = %0h, co = %0h at time = `%0t",a,b,cin,summ,cout,$time); // gate level
#200 $finish;
end
endmodule
。
module FA_gatelevel(a, b, cin, summ, cout);
input a,b,cin;
output summ,cout;
FA_co ins_co(.a(a), .b(b), .cin(cin), .cout(cout));
FA_sum ins_sum(.a(a), .b(b), .cin(cin), .summ(summ));
endmodule
。
module FA_co (a, b, cin, cout);
input a, b, cin;
output cout;
wire ab, bc, ca;
and g0 (a,b,ab);
and g1 (b,c,bc);
and g2 (c,a,ca);
or g3 (ab,bc,ca,cout);
endmodule
。
module FA_sum(a, b, cin, summ);
input a, b, cin;
output summ;
xor g0 (a,b,cin,summ);
endmodule