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我的代碼描述了一個FSM來控制交通信號燈。有四個州,每個州的持續時間都不相同。計數器數字扼腕
只要計數器等於1,計數器就需要多一個時鐘才能切換到下一個值。例如,在狀態1,計數器被編程爲從4到1計數。每個值只需要一個時鐘到 切換到下一個狀態,當狀態變爲下一個狀態時。但是當計數器等於1時,需要兩個時鐘才能更改。
我的程序如下。該計數器在always塊的底部實現:
module HW3(times,A,B,clk,rst,iHand,iChang,s1);
input clk,rst;
output reg [2:0]A,B;
wire oclk;//new freq
reg [2:0] count1,count2,count3,count4;//count times
reg [2:0]times;
reg temp;//control the switch
parameter [2:0]state1=3'd0,state2=3'd1,state3=3'd2,state4=3'd3;
[email protected](posedge clk or negedge rst )
begin
if(!rst)
begin
s1<=state1;
A<=3'b0;
B<=3'b0;
count1<=3'd4;
count2<=3'd2;
count3<=3'd3;
count4<=3'd2;
temp<=1'b1;
end
else
begin
if(temp==1)
begin
temp<=1'b0;
case(s1)
state1:
begin
times<=count1;
A<=3'b001;
B<=3'b100;
s1<=state2;
end
state2:
begin
times<=count2;
A<=3'b010;
B<=3'b100;
s1<=state3;
end
state3:
begin
times<=count3;
A<=3'b100;
B<=3'b001;
s1<=state4;
end
state4:
begin
times<=count4;
A<=3'b100;
B<=3'b010;
s1<=state1;
end
default:
begin
A<=3'b000;
B<=3'b000;
end
endcase
end
else
begin
if(times>1)
times<=times-1;
else if(times==1)
begin
temp<=1'b1;//can't count averagely
end
end
end
end
endmodule
您的代碼有很多很多問題的價值。 [Read This!](http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf) – N8TRO 2014-12-02 07:44:49
我已經修復了你說的問題,但延遲仍然存在 – 2014-12-02 11:22:46
我已將它設置在[EDA Playground](http ://www.edaplayground.com/x/8Ap)。它看起來像所有的國家需要一個額外的時鐘來過渡。將'state'和'times'添加到波形視圖。 – Morgan 2014-12-02 12:06:29