如何在Verilog中將多個數組組合成一個數組？

這裏是我的代碼：如何在Verilog中將多個數組組合成一個數組？

module MIPS_Processor(); 
    reg [7:0] mem [0:4095];  // 4K memory cells that are 8 bits wide 
    reg [7:0] code[0:1023];  // 1K memory cells that are 8 bits wide 
    reg [31:0] registers[0:31]; // 32 registers that are 32 bits wide 
    reg [31:0] PC;    // The program counter 

    initial 
     begin 
      PC = 0; 
     end 

    always 
     begin 
      // 1. Fetch an instruction from memory 
      bit [31:0] instruction = {{code[PC * 8 + 7:PC * 8 + 0]}, 
            {code[(PC + 1) * 8 + 7:(PC + 1) * 8 + 0]}, 
            {code[(PC + 2) * 8 + 7:(PC + 2) * 8 + 0]}, 
            {code[(PC + 3) * 8 + 7:(PC + 3) * 8 + 0]}}; 

      // 2. Increment the program counter register (by the instruction length) 
      PC = PC + 4; 

      // Rest of the code 

    end 
endmodule

我怎麼能結合4個陣列成一個陣列來從該代碼的指令？上面的代碼不能編譯！

編輯：

代碼更改爲以後有什麼建議@toolic：

bit [31:0] instruction = { 
        code[PC + 0], 
        code[PC + 1], 
        code[PC + 2], 
        code[PC + 3] 
};

的是，它不會編譯：

採用Xilinx：

========================================================================= 
*       HDL Compilation        * 
========================================================================= 
Compiling verilog file "MIPS_Processor.v" in library work 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 expecting ']', found ':' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '=' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '{' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 40 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 41 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 42 expecting '.', found ',' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 44 expecting '.', found '}' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: '=' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: 'PC' 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'end', found '+' 
Module <MIPS_Processor> compiled 
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'endmodule', found '4' 
Analysis of file <"MIPS_Processor.prj"> failed. 
--> 

Total memory usage is 274336 kilobytes 

Number of errors : 11 ( 0 filtered) 
Number of warnings : 0 ( 0 filtered) 
Number of infos : 0 ( 0 filtered) 


Process "Synthesize - XST" failed

使用Verilogger極端：

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來源

2012-03-16 Eng.Fouad

作爲題外話，MIPS使用字尋址的存儲器與字節使能，因此改變你的代碼，以便它模擬你的Verilog內存作爲一個單詞陣列將更好地匹配硬件，並將使檢測未對齊的內存訪問更容易在其餘的Verilog代碼。 – markgz 2012-03-16 23:51:05

爲了形成從code存儲器的連續4個字節的指令字：

// 1. Fetch an instruction from memory 
bit [31:0] instruction = { 
         code[PC + 0], 
         code[PC + 1], 
         code[PC + 2], 
         code[PC + 3] 
};

來源

2012-03-16 23:43:20 toolic

+1感謝您的回答，但它不能編譯:( – 2012-03-17 00:08:13

它使用2個不同的模擬器編譯我 – toolic 2012-03-17 00:55:20

請參閱更新 – 2012-03-17 01:06:36

如何在Verilog中將多個數組組合成一個數組？

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