Verilog Xilinx - FPGA板 - 無法實例化三個計數模塊的多個實例

Question

我想實例化我的計數器模塊的三個實例。但是，賽靈思將僅爲我實例化一個計數器，而不是三個計數器。有人知道爲什麼嗎？在RTL原理圖中，第二個兩個計數器在其框圖中直接連接到地，即沒有實現它們的邏輯。我的本地參數是否正確聲明？

我真的很感謝你的幫助。我一直在盯着這個問題好幾個小時。

非常感謝您的幫助。真的很感激。

//Top Level Module: 
`timescale 1ns/1ps 

//Top Level Wrapper module 

module topWrapper(input CCLK, input reset, output clk, output max_tick_Green, output max_tick_Red, output max_tick_Amber); 

    localparam 
     M_Green = 5; 
     M_Red = 3; 
     M_Amber = 2; 

    //Frequency scaling of CCLK 
    //clk is used in the traffic light module and is a scaled version of CCLK 
    //CCLK: Frequency = 50MHz, Period = 20ns 
    //clk = Frequency = 1Hz, Period = 1s 
    //clkscale (frequency scaling parameter) = 1s/20ns = 5x10^7 
    clock clockScalingModule (CCLK, 50000000, clk); 

    //Counter for green light 
    //In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins 
    counter #(.M(M_Green)) countGreen 
     (.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Green)); 

    //Counter for red light 
    //In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins 
    counter #(.M(M_Red)) countRed 
     (.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Red)); 

    //Counter for amber light 
    //In traffic light sequence, change from green to amber after 12 clock cycles = 120s = 2mins 
    counter #(.M(M_Amber)) countAmber 
     (.clk(clk), .reset(reset), .state(1), .max_tick(max_tick_Amber)); 


endmodule 


//Counter module: 

//Counter - modulo M counter - counts 0 to M-1, then wraps around 

module counter 

    //Parameters 
    //M = number of clock cycles the counter counts = max value 
    #(parameter M = 6) 

    //I/O signals 
    (
     input wire clk, reset, state, 
     output wire max_tick 
    ); 

    //Local parameter 
    //N = number of bits in counter 
    //N = ceiling(log2(M)) - definition at end of module 
    localparam N = clog2(M); 

    //Internal signal declaration 
    reg [N-1:0] r_reg; 
    wire [N-1:0] r_next; 

    //Body 
    //Rgister update 
    always@(posedge clk, posedge reset) 
     //Restart counter if reset is High or state is Low 
     //State = Low if this counter's light is not currently on 
     //State = High if this counter's light is currently on 
     if(reset) 
      r_reg <= 0; 
     //Only increment counter if state is High 
     //Only one of red, green, amber states is high 
     else if(state) 
        r_reg <= r_next; 
       else 
        r_reg <= 0; 

    //Next-state logic 
    assign r_next = (r_reg == M) ? 0: r_reg + 1; 

    //Output logic 
    //Max tick = HI when maximum count value is reached 
    //Max tick = LO otherwise 
    assign max_tick = (r_reg == M) ? 1'b1 : 1'b0; 

    //Ceiling log2() function definition 
    function integer clog2; 
    input integer value; 
    begin 
     value = value-1;   
     for (clog2=0; value>0; clog2=clog2+1) 
      value = value>>1; 
    end 
    endfunction 

endmodule 

Answer 1

你的問題是在你的計數器模塊。您的clog2函數返回表示inputvalue-1所需的位數。因此，如果inputvalue恰好是2的冪，則不能用返回的長度表示inputvalue。

這可能不是很清楚，所以讓我們來看看M_amber = 2會發生什麼。在這種情況下，clog2返回1，r_reg是範圍[0:0]，但您需要2位來表示2 = 2'b10。你需要能夠代表2，因爲你的代碼中有支票r_reg == M。所述檢查總是失敗，Xilinx將刪除邏輯並將您的邏輯連接到地。

通常情況下，如果要計算HDL中的N個週期，請從0 to N-1開始計數。因此，如果您將r_reg == M替換爲r_reg == M-1，那麼您的代碼將會正常工作。