差異的uvm_analysis端口之間

Question

能否請您幫助理解之間的功能和明顯的區別：

1. uvm_analysis_export
2. uvm_analysis_port
3. uvm_analysis_imp

我已搜查在互聯網上，有一些解釋，如那些：

• https://verificationacademy.com/forums/uvm/uvmanalysisimp-and-uvmanalysisexport
• https://www.vmmcentral.org/uvm_vmm_ik/files3/tlm1/uvm_analysis_port-svh.html

但我仍覺得需要更多的解釋。有人可以幫忙嗎？

Answer 1

uvm_analysis_port的是出版商，他們播出的交易

uvm_analysis_imp的是用戶，他們會收到交易和調用名爲在其被定義的類‘寫’功能。

uvm_analysis_export可能會更令人困惑，它們被用來暴露層次結構中更高級別的「imp」端口。例如，如果您擁有包含具有analysis_imp的組件的代理程序，並且想要在代理程序的界面級別上提供該「imp」，則可以使用該代理程序。在這種情況下，您聲明並實例化代理類中的analysis_export，然後在connect_phase中將代理的analysis_export連接到內部組件的analysis_imp。

值得注意的是，出口是用於訂閱方面，但在發佈方面，可以以相同方式使用常規uvm_analysis_port。因此，agent可以實例化analysis_ports並將它們連接到內部組件的analysis_port。

這是好事，因爲它可以讓你避免達到分解成層次結構，當你連接部件（這使得維護更加簡單）：

不好：

bus_agent.internal_monitor.packet_port.connect(checker.ref_model.packet_imp) 

好：

bus_agent.packet_port.connect(checker.packet_export) 

它也很好熟悉宏uvm_analysis_imp_decl()。它允許您在組件中使用多個analysis_imp。

Answer 2

此分析端口的優點是用戶可以將數據從單個生產者傳輸到多個使用者，這些使用者在uvm_blocking_put_port的幫助下未歸檔。

這個東西也在圖中解釋。

這裏我提供了示例代碼，以獲得uvm_analysis_port的更多清晰度。

切記：端口連接用於連接兩個或多個獨立組件。

This image gives explanation of uvm_analysis_port

uvm_analysis_port例

class transaction extends uvm_sequence_item; 
    `uvm_object_utils(transaction); 
    rand int unsigned a; 
    rand int unsigned b; 

    function new(string name =""); 
    super.new(name); 
    endfunction 

endclass 


class producer extends uvm_component; 
    `uvm_component_utils(producer); 
    transaction tr_inst; 
    uvm_analysis_port #(transaction) produce_to_consumer_p; 

    function new(string name ="",uvm_component parent); 
    super.new(name,parent); 
    produce_to_consumer_p = new("produce_to_consumer_p",this); 
    tr_inst = new("tr_inst"); 
    endfunction 


    task run_phase(uvm_phase phase); 
    super.run_phase(phase); 
    phase.raise_objection(this); 
// tr_inst.randomize(); 
    `uvm_info(get_full_name(),"Write the data from PRODUCER",UVM_LOW); 
    tr_inst.a = 10; tr_inst.b = 20; 
    produce_to_consumer_p.write(tr_inst); 
    phase.drop_objection(this); 
    endtask 

endclass 

class consumer_1 extends uvm_component; 
    `uvm_component_utils(consumer_1); 
    uvm_analysis_imp#(transaction,consumer_1) write_imp_1; 

    function new(string name ="",uvm_component parent); 
    super.new(name,parent); 
    write_imp_1 = new("write_imp_1",this); 
    endfunction 

    function void write(transaction tr_inst); 
    `uvm_info(get_full_name(),"Got the data in CONSUMER_1",UVM_LOW); 
    `uvm_info(get_full_name(),$sformatf("The value of a = %0d and b = %0d",tr_inst.a,tr_inst.b),UVM_LOW); 
    endfunction 

endclass 

class consumer_2 extends uvm_component; 
    `uvm_component_utils(consumer_2); 
    uvm_analysis_imp#(transaction,consumer_2) write_imp_2; 

    function new(string name ="",uvm_component parent); 
    super.new(name,parent); 
    write_imp_2 = new("write_imp_2",this); 
    endfunction 

    function void write(transaction tr_inst); 
    `uvm_info(get_full_name(),"Got the data in CONSUMER_2",UVM_LOW); 
    `uvm_info(get_full_name(),$sformatf("The value of a = %0d and b = %0d",tr_inst.a,tr_inst.b),UVM_LOW); 
    endfunction 

endclass 

class consumer_3 extends uvm_component; 
    `uvm_component_utils(consumer_3); 
    uvm_analysis_imp#(transaction,consumer_3) write_imp_3; 

    function new(string name ="",uvm_component parent); 
    super.new(name,parent); 
    write_imp_3 = new("write_imp_3",this); 
    endfunction 

    function void write(transaction tr_inst); 
    `uvm_info(get_full_name(),"Got the data in CONSUMER_3",UVM_LOW); 
    `uvm_info(get_full_name(),$sformatf("The value of a = %0d and b = %0d",tr_inst.a,tr_inst.b),UVM_LOW); 
    endfunction 

endclass 

class env extends uvm_component; 
    `uvm_component_utils(env); 

    producer p_inst; 
    consumer_1 c_inst_1; 
    consumer_2 c_inst_2; 
    consumer_3 c_inst_3; 

    function new(string name="",uvm_component parent); 
    super.new(name,parent); 
    p_inst = new("p_inst",this); 
    c_inst_1 = new("c_inst_1",this); 
    c_inst_2 = new("c_inst_2",this); 
    c_inst_3 = new("c_inst_3",this); 
    endfunction 

    function void connect(); 
    p_inst.produce_to_consumer_p.connect(c_inst_1.write_imp_1); 
    p_inst.produce_to_consumer_p.connect(c_inst_2.write_imp_2); 
    p_inst.produce_to_consumer_p.connect(c_inst_3.write_imp_3); 
    endfunction 

endclass 

module main(); 

    env env_inst; 
    initial 
    begin 
    env_inst = new("env_inst",null); 
    run_test(); 
    end 

endmodule 

這裏是鏈接，讓你分析端口更清晰以及uvm_port。

鏈接：http://stackoverflow.com/questions/38085875/where-to-use-uvm-blocking-put-port-and-uvm-analysis-port