內部產生復位的Verilog 2005

想使用頂層的verilog 2005模塊來實現PWM序列：內部產生復位的Verilog 2005

module PWM_ENHANCER (

    input clk, 
    input rst, 
    input sent, 

    //input 
    input [7:0] BUF,          //BUFFER - The PWM reads from it only when 'sent' signal is received, and the current run is done. 

    //output 
    output reg PWM_WAIT, 
    output reg PWM_OUT 
    ); 
reg   [7:0] SAMPLE; 
reg  [7:0] counter; 
reg  WORK; 

[email protected](posedge clk or negedge rst) 

begin 
    if(!rst) 
    begin 
     WORK <= 1'b0;        //When receiving a reset, everything zeroes. 
     counter <= 8'b0; 
     PWM_WAIT <= 1'b1; 
     SAMPLE <= 8'b0; 
     PWM_OUT <= 1'b0; 
    end 
    else if (sent == 1 && WORK == 0) 
    begin    //If the pwm was OFF, and i received sign from the array, i start running PWM. 
     SAMPLE <= BUF; 
     WORK <= 1'b1; 
     PWM_WAIT <= 1'b0; 
    end 
    else if(WORK == 1) 
    begin        //The running block - sending '0' and '1' as needed. 
      if ((counter <= SAMPLE) && (SAMPLE != 0)) 
      begin 
       PWM_OUT <= 1'b1; 
       counter = counter + 1'b1; 
      end 

      else if (counter > SAMPLE) 
      begin 
       if (counter == 8'b11111111) 
       begin 
        counter <= 8'b0; 
        WORK <= 1'b0; 
       end 

       else 
       begin 
        counter = counter + 1'b1; 
        PWM_OUT <= 1'b0; 
       end 
      end; 
      if(counter == 200) 
      begin      // 50 cycles before the end, PWM sends acknowledge for the array to send the next sample. 
       PWM_WAIT <= 1'b1; 
      end 
    end  

    else 
    begin 
     ;               // if NOT receiving 'sent' from the array - the PWM does nothing. 
    end 

end 
endmodule

編譯時接收到的錯誤：

「在頂部設計單元內部產生的復位‘PWM_ENHANCER’不是允許「。

如何在@always語句中包含重置？

來源

2016-11-27 ducklock

您需要指定您用於編譯的工具。這不是一個Verilog語言問題 –

似乎有點不同。請發佈代碼，你已經實例化了這個模塊。 –

兩個可能性（二者合成相關）：

你的合成器需要額外的手保持的異步復位

if(!rst) begin 
    WORK <= 1'b0; 
    counter <= 8'b0; 
    PWM_WAIT <= 1'b1; 
    SAMPLE <= 8'b0; 
    PWM_OUT <= 1'b0; 
end 
else begin 
    // other logic in here 
end

你的標準單元庫缺乏與異步復位/預置觸發器。 FPGA的異步復位/預設傾向於有限數量的觸發器。有些FPGA沒有。如果是這種情況，可以做的最簡單的事情是將異步復位更改爲同步復位，方法是將始終塊的頂部更改爲[email protected](posedge clk)（省略or negedge rst）。
如果您在FPGA上，那麼您可能需要添加initial模塊來初始化寄存器的默認值。

來源

2016-11-28 22:33:04 Greg

內部產生復位的Verilog 2005

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