module encoder (op, in, clock, reset);
//$display("We are in initial procedural block");
input [15:0] in;
input clock, reset;
output [3:0] op;
wire [15:0] in;
wire clock, reset;
reg [3:0] op;
always @ (posedge clock)
begin
$display("We are in initial procedural block");
if (reset)
begin
$display("we are in the reset condition");
op = 0;
end
else
begin
case(in)
16'h0002: #1 op = 4'b0001;
16'h0004: #1 op = 4'b0010;
16'h0008: #1 op = 4'b0011;
16'h0010: #1 op = 4'b0100;
16'h0012: #1 op = 4'b0101;
16'h0014: #1 op = 4'b0110;
16'h0018: #1 op = 4'b0111;
16'h0020: #1 op = 4'b1000;
16'h0022: #1 op = 4'b1001;
16'h0024: #1 op = 4'b1010;
16'h0028: #1 op = 4'b1011;
16'h0030: #1 op = 4'b1100;
16'h0032: #1 op = 4'b1101;
16'h0034: #1 op = 4'b1110;
16'h0038: #1 op = 4'b1111;
16'h0040: #1 op = 4'b0000;
default : $display("DEFAULT!!!");
endcase
end
end
endmodule
module encoder_tb;
input in, reset, clock;
output op;
reg [15:0] in = 16'h0000;
reg reset, clock;
wire [3:0] op;
//internal variable
reg [15:0] incremental_value = 16'h0002;
initial
begin
$monitor("time = %g,\tclock = %d,\tin = %h,\top = %b",
$time, reset, in, op);
$display("We are in initial procedural block");
in = 0;
reset = 0;
clock = 0;
op = 0;
#1 clock = !clock;
#10 reset = !reset;
#5 in = in + incremental_value;
#100 $finish;
end
always
begin
#1 clock = !clock;
#10 reset = !reset;
#5 in = in + incremental_value;
end
encoder_tb test_bench (.op(op), .in(in), .clock(clock), .reset(reset));
// Waveform Generation
initial
begin
$dumpfile("encoder.vcd");
$dumpvars(0,op,in,clock,reset);
end
endmodule
上面我試圖創建一個16位輸入到4位輸出編碼器。我能夠編譯我的代碼沒有任何錯誤,但在[iverilog encoder_tb.v -o編碼器] & [vvp編碼器vcd]命令後,它不給我任何提示,即使我給了$ monitor和幾個$ display語句,我可以想到任何地方。我試圖找到錯誤,但由於我對此很新,所以我無法調試。任何和所有幫助表示讚賞。 謝謝。Verilog代碼編譯沒有錯誤,但沒有輸出
顯示陳述並非對調試任何複雜的RTL真的足夠了。你應該看看使用波形觀察程序。 * Xilinx ISE webpack *是一個非常有用的免費軟件,可能會引起您的注意,或者可能* iVerilog * – Tim
該代碼給我帶來了2個模擬器的編譯錯誤。你確定這是你的確切代碼嗎? – toolic
@Tim - 我已經包含/嘗試使用命令$ dumpfile和$ dumpvars使用GTKwave生成波形,但我無法生成任何波形。謝謝 – user3043882