無法解決錯誤，VHDL，語法錯誤，但我沒有看到它

Question

我無法設法解決這個乘法器中的錯誤。我是VHDL新手，所以它可能是一個非常愚蠢的問題（我試圖解決這個問題，但它似乎並沒有成功）它說：Error: C:/modeltech_6.5/examples/pipe.vhd(41): near "label": syntax error

我想爲我的管道乘法器項目

entity mult_secv is 
    generic(
    Na : integer := 8; 
    Nb : integer := 8; 
    Nscnt : integer := 4 
    ); 
    port(
    iCLK : in std_logic; 
    iRST : in std_logic; 
    iDV : in std_logic; 

    ia  : in std_logic_vector(Na-1 downto 0); 
    ib  : in std_logic_vector(Nb-1 downto 0); 

    oDV  : out std_logic; 
    oDATA : out std_logic_vector(Na+Nb-2 downto 0) 
    ); 
end mult_secv; 

architecture produs of mult_secv is 
    type my_array1 is array(1 to 8)of std_logic_vector(Na+Nb-2 downto 0); 
    type my_array2 is array(1 to 8) of std_logic_vector(Nb-1 downto 0); 
    type my_array3 is array(1 to 8) of std_logic; 
--8 stagii pentru a se calcula tot produsul 
    signal sa, srez : my_array1; 
    signal sb : my_array2; 
    signal dv : my_array3; 
    constant scntmax : integer:=8 ; 

begin 
    -- for each pipeline stage 
label : for scnt in 1 to scntmax generate ---> CAUTA SINTAXA PENTRU GENERARE DE COMPONENTE IDENTICE 

process(iCLK,iRST) 
begin 
    if iRST= '1' then 
    sa <= (others => (others => '0')); 
    elsif rising_edge(iCLK) then 
    -- first stage 
    if (scnt = 1) then 
     sa(scnt) <= (Na+Nb-2 downto Na => ia(Na-1)) & ia; ---se bordeaza cu bitul de semn daca e negativ 
    -- other stages 
    else 
     sa(scnt) <= sa(scnt-1)(Na+Nb-3 downto 0) & '0'; --altfel se shifteaza sa 
    end if; 
    end if; 
end process; 


process(iCLK,iRST) 
begin 
    if iRST='1' then 
    sb <= (others => (others => '0')); 
    elsif rising_edge(iCLK) then 
    if (scnt = 1) then 
     sb(scnt) <= ib; 
    else 
     sb(scnt) <= '0' & sb(scnt-1)(Nb-1 downto 1); --se shifteaza sb 
    end if; 
    end if; 
end process; 

process(iCLK,iRST) 
begin 
    if iRST='1' then 
    srez <= (others => (others => '0')); 
    elsif rising_edge(iCLK) then 
    if (scnt = 1) then 
     if ib(Nb-1)='1' then 
    srez(scnt) <= not (ia & (Nb-2 downto 0 => '0')) + '1'; --daca este negativ 
     else 
     srez(scnt) <= (others => '0'); --in primul stadiu 
     end if; 
    elsif sb(scnt-1)(0)='1' then   
     srez(scnt) <= srez(scnt-1)+sa(scnt-1); 
    else  
     srez(scnt) <= srez(scnt-1); 
    end if; 
    end if; 
end process;  

process(iCLK,iRST) 
begin 
    if iRST='1' then 
    dv <= (others => '0'); 
    elsif rising_edge(iCLK) then 
    if (scnt = 1) then 
     dv(scnt) <= iDV; 
    else 
     dv(scnt) <= dv(scnt-1); 
    end if; 
    end if; 
end process; 

end generate label; 

oDATA <= srez(scntmax); 
oDv <= dv(scntmax); 

end; 

任何人都可以幫忙嗎？

Answer 1

label是VHDL中的保留關鍵字。正如你可以在你的代碼高亮上面看，它是藍色:)

Answer 2

ghdl報道：

ghdl -a mult_secv.vhd 
mult_secv.vhd:31:1: unexpected token 'label' in a concurrent statement list 
mult_secv.vhd:37:3: unexpected token 'elsif' in a concurrent statement list 
mult_secv.vhd:42:5: unexpected token 'else' in a concurrent statement list 
mult_secv.vhd:44:9: ';' is expected instead of 'if' 
ghdl: compilation error 

這使得它更清楚是什麼問題。

我經常發現使用多個編譯器編譯源代碼很有用;每個人都有自己的長處和短處。